(Please visit the site to view this file)Here I have attached the schematic file of the board. I have ensured that my SCLK is fast enough to not mess up the DRDY timing, DRDY is 500SPS and SCLK is fast enough to comfortably read 27 bytes of data from the ADS. Register initializations: ADS_WREG(ADS1298_CONFIG1_REG, 0x06); //Data Rate = Fmod/1024, Low Power Mode ADS_WREG(ADS1298_CONFIG2_REG, 0x10); //Test signals are generated internally ADS_WREG(ADS1298_CONFIG3_REG, 0xD4); //PD_REFBUF enable, VREFP is set to 2.4V, RLD_REF is set, RLD_REF is fed externally, RLD_BUF enabled, RLD_sense is off, RLD is connected ADS_WREG(ADS1298_LOFF_REG, 0x02); //Do not use ADS_WREG(ADS1298_CH1SET_REG, 0x50); //Gain = 8, Normal electrode input ADS_WREG(ADS1298_CH2SET_REG, 0x50); ADS_WREG(ADS1298_CH3SET_REG, 0x50); ADS_WREG(ADS1298_CH4SET_REG, 0x50); ADS_WREG(ADS1298_CH5SET_REG, 0x55); //Gain = 8, Test signals ADS_WREG(ADS1298_CH6SET_REG, 0x55); ADS_WREG(ADS1298_CH7SET_REG, 0x65); //Gain = 12, Test signals ADS_WREG(ADS1298_CH8SET_REG, 0x65); ADS_WREG(ADS1298_RLDSENSP_REG, 0x00); ADS_WREG(ADS1298_RLDSENSN_REG, 0x00); ADS_WREG(ADS1298_LOFFSENSP_REG, 0x00); ADS_WREG(ADS1298_LOFFSENSN_REG, 0x00); ADS_WREG(ADS1298_LOFFFLIP_REG, 0x00); ADS_WREG(ADS1298_GPIO_REG, 0x00); //GPIO OUTPUT ADS_WREG(ADS1298_PACE_REG, 0X00); ADS_WREG(ADS1298_RESP_REG, 0XF0); // Respiration phase = 90, Internal Respiration of with user generated signals ADS_WREG(ADS1298_CONFIG4_REG, 0X00); //64 kHz modulation clock ADS_WREG(ADS1298_WCT1_REG, 0x00); ADS_WREG(ADS1298_WCT2_REG, 0x00); I am sorry, I dont have any images of waveforms! One more detail that i think may be of interest is that - When i initialize the ADS, VCAP1 capacitor charges to about 1.019V no matter how much delay I set in the code. Only when I start reading and DRDY halts, VCAP1 voltage exceeds 1.1V (as i observed in the datasheet). Can this be the issue?
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