Hi Ebenezer, Thanks for your reply. A few questions: 1. Would triggering sysref multiple times be equivalent to this technique? 2. What is this timing adjustment and what registers would I program? 3. Could you please provide a configuration file for continuous sysref operation? --- LMFS = 2441 Line Rate = 9.8304 Gbps Lanes Active: RX2 and RX3 We have DACs on: DCLKOUT0 SDCLKOUT1 (DAC 0 - Non functioning) DCLKOUT8 SDCLKOUT9 (DAC 1 - Non functioning) DCLKOUT10 SDCLKOUT11 (DAC 2 - Functioning) DCLKOUT12 SDCLKOUT13 (DAC 3 - Functioning) and the FPGA on: DCLKOUT4 SDCLKOUT5 Unconnected: DCLKOUT2 SDCLKOUT3 DCLKOUT6 SDCLKOUT7 ---
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