Forum Post: RE: Linux/DDC2256AEVM: ddc2256
Hi Bugra, How are you? Thank you for using DDC2256AEVM . For your reference design using Altera FPGA, I will forward it to our system engineer in these couple days and will reply to you, too. Thank...
View ArticleForum Post: RE: ADS124S06: ADS124S06 Unused REFN0
Hi Bob, Thank you very much for your clarification. Very helpful. Masa
View ArticleForum Post: RE: ADS124S06: ADS124S06 Read Data Direct setting
Hi Bob, THANK YOU VERY MUCH for your series of answers!! Masa
View ArticleForum Post: RE: ADS114S08: Data output from ADS goes to zero intermittently
Dear Bob, You are right about the power supply noise. Our SMPS was very noisy we replace it and all problems were resolved. Also the STATUS register which we were getting spurious values also stopped....
View ArticleForum Post: RE: CCS: AFE4900 initial
Hello, Since we already discussing this topic in other thread, I am closing this thread. Thank you. Regards, Sanjay R. Pithadia
View ArticleForum Post: DAC6573: Maximum value of short-circuit current
Part Number: DAC6573 Dear Team Could you please let us know the maximum value of short-circuit current at the both condition Vdd=3V and 5V? Best Regards, Hirokazu Takahashi
View ArticleForum Post: I don't have a part number
Hello , After installing the Delta Sigma Software and device package for ADS124S08 and when I connected the USB to the board,I have a problem in detecting the hardware. I uninstalled the device package...
View ArticleForum Post: RE: AFE4300EVM-PDK: problem connecting
Dear Pavreen, the solution was to go to Windows 7. Perhaps it is a good idea to have a GUI available for windows 10 too, but as this development kit is on its way out I can imagine this will not happen...
View ArticleForum Post: RE: ADS1198: ADA1198 sampling rate variation and signal...
Hi Alex Thank you for your reply. Attached are the data files (Please visit the site to view this file)(Please visit the site to view this file)f digital output signals for 125Hz and 250Hz input...
View ArticleForum Post: RE: ADC12DJ3200EVM: FMC+ to FMC adapter for ADC12DJ3200EVM
Hi Tom Please accept my e2e user connection request, then you can send me a PM including your number. Best regards, Jim B
View ArticleForum Post: RE: TSW14J56EVM: Utilizing SYSREF Input to FPGA to Synchronize...
Hi Russell It is best to have the FPGA device clock and SYSREF generated on the same board. For that reason I recommend keeping the current configuration with the SYSREF source on the ADC board. Best...
View ArticleForum Post: RE: ADS127L01: synchronized data acquisition of multiple...
Hello, Welcome to TI's E2E Community. Answers to your questions. 1. The voltage on each of the input pins, AINP, AINN, must always be between AGND and AVDD for normal operation, and ABS max of...
View ArticleForum Post: RE: ADS54J66: SPI, 24b vs 32b, page selection and EVM config files.
Jake, I assume you are referring to the SDOUT pin, correct? The level of this signal should typically be at DVDD. Is your DVDD supply at 1.9V? What are you driving with this signal? Regards, Jim
View ArticleForum Post: RE: ADS131A02: DRDY data line not behaving as expected
Eddie, That's great. I'm glad you got it working with some reasonable data output. If you have any other questions, feel free to post back. Joseph Wu
View ArticleForum Post: RE: DAC38RF80EVM: LMK04828 SYSREF(P, N) outputs, Rev E schematic...
Atin, This was done on purpose to make the routing easier on the EVM. This is not a problem since there is only one device in this link. The JESD204B standard is just looking for a rising edge on...
View ArticleForum Post: RE: DAC38J84: FIFO Errors
Hi Ebenezer, Thanks for your reply. A few questions: 1. Would triggering sysref multiple times be equivalent to this technique? 2. What is this timing adjustment and what registers would I program? 3....
View ArticleForum Post: RE: Linux/DDC2256AEVM: ddc2256
Hi Bugra, I would like to take this conversation offline since the device is under NDA. I will send you an email shortly.
View ArticleForum Post: RE: DAC38RF80EVM: System Clock Configuration
Jared, I am not familiar with the VCU108, but we have interfaced the DAC EVM with several other Xilinx platforms. If this board can use FMC pins D4/D5 for the device clock, pins F10/F11 for SYNC, and...
View ArticleForum Post: RE: ADC12DJ3200EVM: Storing more than 10 million samples
Hello Sai I think there may be a bug in the current version of firmware being loaded with JMODE2. If you are using a TSW14J57EVM Rev E board and have the latest version of HSDC Pro then you can try the...
View ArticleForum Post: ADS1255: SPI clock SCLK duty spec
Part Number: ADS1255 Hi Experts, There is no spec definition for SPI clock duty. Can we understand that we do not care about clock duty and only follow the spec on "TIMING CHARACTERISTICS FOR FIGURE...
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