Hi Reid, What you're seeing is fairly consistent with what I'd expect... The falling edge of /DRDY is signaling that the conversion has completed. Looking at the second image, it looks like the time between falling edges is very consistent. I expect this because the ADC's conversion processes is mostly controlled by the 4.096 MHz, fCLK. The rising edge of /DRDY is triggered by the first SCLK falling edge (and perhaps by the first fCLK after this SCLK). This signal is coming from MCU and the fact that the the /DRDY rising edge is drifting tells me that there is some variation in the propagation of the /DRDY interrupt to the MCU's SPI peripheral, and between the multiple clocks used to drive all of these signals. [quote user="Reid Dorrance"]Does the data from the ADS1282 ever change or re sample during the duration of the data ready pulse? We are under the impression as soon as the data ready line falls it stores a sample and keeps it for the duration?[/quote] The ADC has an output shift register that loads in the most recent conversion result when the /DRDY signal goes low. This result is stored until the next /DRDY falling egde when it gets over-written; hence avoid reading data during a /DRDY falling edge. However, between /DRDY falling edges the data will not not be updated. [quote user="Reid Dorrance"]The figure 56 in 9.26 shows 4 bytes of data read. But what we seen with the part is that we need to read 5 bytes and discard the first byte. i.e we initiate 5 byte reads, B0, B1, B2, B3, B4, discard B0 keep B1,B2,B3,B4 with B1 as MSB and B4 as LSB. Is 5 Byte read correct or is this the source of our jitter issues?[/quote] I don't think reading five bytes should affect the /DRDY jitter, just when you start reading the data it will trigger /DRDY to go high again. If you are using RDATAC mode and sending 0x00 four times to clock out the data, there shouldn't be a need to send a 5th byte. Are you getting data that appears to be invalid? If so, would you be able to attach a file that shows the raw (unprocessed) ADC data (as hex or integer values). Do keep in mind that the output codes are signed 2's compliment data and that the last bit of data is a redundant sign bit. From your previous post you had also asked... [quote user="Reid Dorrance"]When is the data ready to be read, is it directly after the pulse goes low or is it still sampling data when the SPI transactions are happening?[/quote] Data is ready to be read after /DRDY goes low. However, this is a delta-sigma ADC that is continuously oversampling the input; therefore, the input will be getting sampled while you clock out the data.
↧