Part Number: DDC114 Hi Team, My customer is using the DDC114 and has some questions I'd like your feedback on. The first is around the differential signals for the serial interface of the chip: DCLK, /DCLK, DOUT, /DOUT. If we have a solid ground, how important is the differential signaling regarding noise coupling? I know that's a loaded question, but is it recommended as best practices in general or is it to address long data bus traces or converters at the end of cables? Second, we have generated a clock for the DDC by cheating in the past taking our resonator sine wave into a logic buffer chip to convert to a square wave. We don't like this because the resonator and oscillator have a longer signal trace to drive, as well as probably more jitter due to this configuration. So they have opted in a new revision to use a small MEMS 4MHZ oscillator right next to the DDC and then use a flip flop to synchronize the serial data clock with the local oscillator. In the datasheet it mentions for best performance to use the main MCU system clock to also drive the DDC, but I have a feeling the previous setup converting the sine to a square pulse train is not anywhere near an ideal system clock. So, I'd like to hear your thoughts on this. Thanks, Mitchell
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