Hi Mitchell, How are you? For the customer's first question about the differential pins: DCLK, nDCLK, DOUT, nDOUT, DIN, nDIN as the DDC114 data sheet page13 mentioned these complementary signals are designed to help reduce the digital coupling. (Note: that means if we don't use those complementary signals then the digital "noise" must go through DGND instead of its differential pin. Then when the heavy "noise" working on the DGND, it might be very easy to couple to the AGND and also will affect the analog inputs.) Also another concern for the differential signal traces layout is every differential pair traces such as used for long bus or cable. The other question is for your input clock. Please ensure the master clock CLK is synchronized with CONV and DCLK (nDCLK) and make sure the clock signals avoid overshoot or ringing (according to the data sheet mentioned). Clock jitter may not be an issue since A/D Converter starts to work when the integrator has been settled down and becomes a DC signal. Thank you! Best regards, Chen
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