Hi Vladica, Thank you for your question for ADS52J90 device. Yes, All the output data from LVDS mode (such as DOUTs, FCLK, and DCLK) are sent out together and synchronously from ADS52J90 (as long as all the trace lengths are matched.) which is totally different from JESD mode. such as: 1) All CML OUT signals are from ADS52J90 and will be sent to FPGA (so for these trace lengths needed to be matched.) 2) CLK, SYSREF (both used for ADS52J90 ) are coming from LMK to ADS52J90 (so these two trace pairs length must be matched.) 3) also another CLK, SYSREF, GTXCLK (they are used for FPGA) are coming from LMK to FPGA (so these three trace pairs length must be matched.) However, #1, #2, and #3 these three options seem like they don't need to be matched with each other when using JESD mode. Yes, I will continue to confirm this question with our group engineer. Thank you! Best regards, Chen
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