Hi Keshava, How are you? Thanks for more detail information. By the way, when you are capture the SDOUT signal, please notice its data sheet's spec: ======================= DIGITAL OUTPUTS (SDOUT) High-level output voltage (typ) 1.8 V Low-level output voltage (typ) 0 V ======================= So please check on your FPGA voltage setting for SDOUT. It is not the same as SCLK, SDATA and SEN voltage settings. Thank you! Best regards, Chen
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