Hello Hamamoto-san, Thank you for sharing the additional data. The customer looks to be operating the TSC2046 more closely to what's defined in Figure 9 with a very extended acquire phase to help with input settling while still using the large 100nF input capacitors. We haven't seen the TSC2046 clocked this way and are not sure if there are any repercussions of doing so. Most customers slow down the entire digital communication stream to increase acquisition timing but since the communication seems to work with the exception of the PENIRQ function this doesn't appear to cause issues in their application. In regards to the PENIRQ functionality the new images show that the X+ fall time is the main determining factor for the PENIRQ time period. The PENIRQ signal will go LOW once the X- input is pulled below the logic threshold for the buffer that connects to the PENIRQ level shifter (see Figure 9 below). The fall-time of the X+ input will be based on how fast the Y- driver can discharge the 100nF capacitance on the X+ input through the touch-panel resistance. The reason this behavior is easier to see on after the X-channel measurement is that depending on the X position the X+ input voltage is charged to different levels before the power down drivers (Y-) become active.
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