Hello Sander, Sergio, and Koen,
My responses in color by <HH 4/22/14>:
1) We also have some problems implementing the power supply for this device. There is a relation defined for the different power supplies. VDDD should be greater then VDDA and VDDD should be greater then VDDLVDS. And then some schematic is drawn in figure 3 how to do this. But that is all that I find in the datasheet.
<HH 4/22/14>: The datasheet calls this out on page 8:
VDDD ≥ VDDA,
VDDD ≥ VDDLVDS
So, VDDD can be equalor greater than VDDA (not just greater than). The easiest way to implement this is by using a single LDO for all 3 power supplies (as Figure 3 shows).
2) Are there tolerances on this rule?
Is it only for power sequencing (can we use different regulators for this)?
What are the values of the components in figure 3 ?
What is the maximum ripple allowed on this device? (if I follow the operation conditions then the chip will work with a ripple of 0.6V, I don't find the PSRR either)
<HH 4/22/14>: You can use separate regulators but there is no advantage to this and you must comply with the relationships shown above ( ≥ ).
It is understood that high speed, high resolution ADC devices would not Precision type PSRR ratings. It is expected that the LDO / linear-regulator used to generate the supplies would have low ripple ( < 25mVpp).
3) Do you have a user-manual describing more in detail the operation mode?
<HH 4/22/14>: Unfortunately No.
If you post your questions here, I'll try to respond thoroughly and quickly.
Regards,
Hooman