Part Number: DAC3482 I wonder how to declare PLL locked. According to the datasheet, PLL alarm(REG5) does not work properly for ID 100b or any earlier. That is my case. Alternatively as recommended, I'm looking at "pll_lfvolt" of REG24. However, it is always read 000b. It should be between "010" and "101" for optimal lock range. But the signal at the frequency in interest is super clean. I already tried all possible values of "pll_vco". However "pll_lfvolt" stayed the same. What should I look in? The signal is clean, but my gut feeling tells me to make it clear. Configuration parameters are as follows. f_DATA = 92MHz, Interpolation = 8x, Input data = baseband signal, f_OUT = 140MHz, PLL = Enabled, Full Mixer = Enabled f_REFCLK = 368MHz, f_DACCLK = f_DATA x 8 = 736MHz, f_VCO = P x f_DACCLK = 3680MHz (P=5), N = 8, M = 8, Single charge pump, pll_vco = 110101b = 53 Is there anything wrong with the configuration above? best regards, Shim
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