Hi Chen, thank you for your answer! Regarding the second question: The way I understand it now is, that the digital output delay of setup 2 from above is ~420us, correct? These are the settings from the device during the tests stated above: EQ_EN=1 LNA_GAIN=3 PGA_GAIN=5 FILTER_BW=1 HIGH_POW_LNA=1 EQ_EN_LOW_FC=1 HPL_EN=0 HEADER_MODE=0 DIV_REG=1 (Clock divider 2, 50MHz/2=25MHz) Therefore HF_AFE_CLK=0 DIV_EN=1 DIV_FRC=1 SE_CLK_MODE=1 (single ended clock used) DSYNC_EN=1 DSYNC1_START_LOW=1 DELAY_COUNT=1 MULT_EN=0 STAT_EN=0 All channels activated, none disabled. For decimation 2: DECIMATE_2_EN=1 FILT_EN=1 Filter set 1 written to C1-C6 For decimation 4: DECIMATE_4_EN=1 DECIMATE_2_EN=1 FILT_EN=1 Filter set 1 written to C1-C6 If you need any more information, please let me know! One additional question I encountered during the last days (currently I have no means of measuring it): What is the output of DCLK, if decimation is active? For example setup 4 from above (25MHz AFE_CLK and Decimation factor 4): Is DCLK outputting 100 MHz (4xAFE_CLK) or 25 MHz (4xAFE_CLK/4)? Kind regards, Tobias
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