Hi Jim, I'm agree with you, because I've observed that the delta phase between the two channels is constant. The problem is that this delta phase in not good for the system and I've tried to modify the SYSREF delay externaly to the ADC (using the internal TAP of the FPGA) of one or two ADC_CLK cycles. Changing the SYSREF position, I'll suppose that the SYSREF position change and the ALIGNED = 1 and REALIGNED = 1 . Instead the ALIGNED = 1 (first I had resetted), the REALIGNED = 0 and the delta phase is the same. Do you think that the ADC sees the same SYSREF? Thanks in advance. Best Regards, Daniele
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