Part Number: DAC38RF80EVM Hey all, So after receiving previous direction on how to test the NCOs and subsequent output of the DAC before interfacing with the FPGA(see: e2e.ti.com/.../776799) , I began testing and playing around with the capabilities of the NCOs. While there appears to be no constraint on their frequency (other than the max frequency output being half that of the frequency of the sampling clock), I've ran into an issue where they aren't outputting anything when the sampling frequency is above the default value of 4915.2 MHz. Our clock, the LMX2595 , is capable of producing the max sampling clock frequency of 9GHz and below. I don't believe it's a power issue of the clock input signal. We also have made the modifications for to use a differential clock on the DAC EVM board. Do you have any ideas what might be causing the issue? Thanks, Jared
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