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Forum Post: RE: AFE5808A part ADC output in offset binary and 2's complete format

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Chandu, From the DS, page 30: Users can write the required VALUE into register bits which is Register 5[13:0]. Then the device will output VALUE at its outputs, about 3 to 4 ADC clock cycles after the 24th rising edge of SCLK. So, the time taken to write one value is 24 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern will take approximately 128 × (24 SCLK clock cycles + 4 ADC clock cycles). NOTE Only one of the above patterns can be active at any given instant. The output of the device would be: 0x3FFF,0x3FFF,0x3FFF,0x3FFF,0x3FFF,..... 0x2000, 0x2000,0x2000,0x2000,0x2000,.... 0x3000, 0x3000,0x3000,0x3000,0x3000,...... 0x1900,0x1900,0x1900,0x1900,.... This is independent of 2's complement or Offset binary. The number of repetitions of each value depends on the speed of the SPI, as stated above. The fastest refresh rate possible would be 24 SCLK cycles + 4 ADC clock cycles Thanks, Chuck Smyth

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