Hi Hooman I am trying to figure out the same issue. The specific signals can be found on page 24 of the LM96511 Data sheet. The signals of interest are ADC BCLK (bit clock) and the ADC WCLK (word clock). Once the BCLK has been used to deserialize the LVDS data into the FPGA the word clock is used to capture the complete word (or data sample) on the sample boundary. Typically it will be done synchronously with respect to the bit clock. There is however no identifiable relationship in the datasheet between the BCLK and the WCLK so there is no deterministic way to do this without meta-stability occurring. Is this relationship published or available? Many thanks Steven
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