Hi Hooman The only relationship shown is tDWS (Data edge to Word edge skew). The real issue here is how to use the WCLK in the FPGA to frame a complete sample (LSB to MSB). We have coded the LVDS deserializer to use to BCLK to capture the data. So all internal parallelized data is synchronous to the BCLK. SDC (Synopsis design constraints) scripts are created to direct the Quartus fitter to place and route the logic so it meets the timing requirements of these signals from the ADC. There is no defined relationship between the BCLK and the WCLK. Thus there is no deterministic relationship between the two signals and we have to treat WCLK as if it is asynchronous to the BCLK. If there was a guaranteed relationship (as there is between the data and the BCLK) then we could guarantee valid setup / hold timing of WCLK with respect to DCLK. This would make syncronizing WCLK to BCLK possible. This is important because we use a sync'ed delayed version of WCLK to capture the input data in a shift register on the LSB / MSB boundary. Thanks for the assistance. Regards Steven
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