Forum Post: RE: LM96511 -- fclk and bit clk relationship
Hi Steven, Do you mind marking up this timing diagram to state what is the exact timing between ADC BCLK and ADC WCLK you are looking for that is not in the LM96511 datasheet? Regards, Hooman
View ArticleForum Post: RE: LM96511 -- fclk and bit clk relationship
Hi Hooman The only relationship shown is tDWS (Data edge to Word edge skew). The real issue here is how to use the WCLK in the FPGA to frame a complete sample (LSB to MSB). We have coded the LVDS...
View ArticleForum Post: RE: Interfacing AFE5804 with TSW 1405
Hi, Yes I am familiar with LabView so a LV soultion would be great. Thanks.
View ArticleForum Post: RE: LM96511 -- fclk and bit clk relationship
Hi Steven, My understanding of this device interface is that the WCLK is just another data line that is used to indicate the frame of the data so that the digital sample can be re-constructed AFTER the...
View ArticleForum Post: RE: Interfacing AFE5804 with TSW 1405
Anup, In the HSDCPro folder there are 3 options(HSDCPro running in the background): Labview: 1. C:\Program Files (x86)\Texas Instruments\High Speed Data Converter Pro\Automation Function APIs\LabVIEW...
View ArticleForum Post: TSW1400 Firmware Source for AFE5809EVM
Hello, I have got a AFE5809EVM recently, and I am quite satisfied with its performance after evaluation it with the TSW1400 platform. May I have a copy of its FPGA firmware source code for TSW1400 as a...
View ArticleForum Post: RE: TSW1400 Firmware Source for AFE5809EVM
Ang, Please see the firmware reference. This is distributed AS IS and will not be supported by our group.
View ArticleForum Post: RE: VSP2582 Test Enable bit?
Chris, As you may or may not know this family of devices are not recommend for new designs (aka NRND). However I was able to get some data for you in regards to the VSP2582. Could you please contact me...
View ArticleForum Post: Can LM96511 run slower than 40MSPS?
The LM96511 data manual says the sampling rate has to be between 40 and 40.5 MSPS. Can it run slower? I need to simultaneously sample all 8 channels for 8 milliseconds, and I can't find a way to buffer...
View ArticleForum Post: transistor-type photo-sensor with AFE44xx?
Hi, I was wondering if you could help me while Praveen is on vacation. Do you know if we can use a transistor-type photo-sensor with AFE44xx? For instance,...
View ArticleForum Post: RE: transistor-type photo-sensor with AFE44xx?
Rodger, We have done some preliminary evaluations on NJL5501R (phototransistor with red and IR LEDs) with AFE44x0. Refer to the e2e post below for more information: e2e.ti.com/.../285068
View ArticleForum Post: VSP2262Y Pin Map
Hello, Could someone know me Pin Map (Top View) of VSP2262Y? Thanks in advance. Best regards, Kenichi Tashiro
View ArticleForum Post: RE: VSP2262Y Pin Map
I just sent you the full datasheet on the VSP2262 device.Regards,Kurt Eckles
View ArticleForum Post: RE: TSW1400 Firmware Source for AFE5809EVM
Chuck, Could you please renew the firmware share? We are using AFE5809 with Altera FPGA however the de-serdesed data is not very stable. So any reference code would be very helpful. Thanks a lot! B.R....
View ArticleForum Post: RE: TSW1400 Firmware Source for AFE5809EVM
What Chuck shared is a actually a firmware which supports many different ADCs (including the parallel LVDS ones). It deserializes the D1-D8 and FCLK as data input with a deserialization factor of 4....
View ArticleForum Post: RE: TSW1400 Firmware Source for AFE5809EVM
Hi Ang, I see and the de-serdes process is the thing I want to refer to . Could you send me a copy via e-mailing to xycfwrj@gmail.com? Thanks a lot! B.R. River
View ArticleForum Post: RE: TSW1400 Firmware Source for AFE5809EVM
Hi River, The firmware in this thread is basically the same as what I have got: I also found Stratix IV Handbook Chapter 8 High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices helped me...
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