Hi Steven, My understanding of this device interface is that the WCLK is just another data line that is used to indicate the frame of the data so that the digital sample can be re-constructed AFTER the data has been passed into the FPGA core. I do not think it should be used as a deserializer frame clock. I think the WCLK should have an identical digital receiver/DESER as all the output data lines. I would assume that the tS and tH would apply to the WCLK as well. The tDWS spec is specifying the worst case differences between the WCLK and a data line. Regards, Josh
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