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Forum Post: RE: LM98725 - PLL Locking

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Hi Christian, The latency through the device from INCLK to CLKOUT output will vary somewhat from part to part due to process variability, random mismatch, etc. For this reason you must use the CLKOUT output from each IC to capture the DOUTx data from that IC. Please note that the spec for t CRDO in the datasheet varies from 2 to 9 ns with a nominal value of 4.5ns. If CLKOUT is at 60 MHz, the high and low times are only 0.5 x 1/60 MHz, or 8.3ns. Even when using the CLKOUT and DOUTx from the same chip, data capture can be somewhat challenging and may require delay tuning of the data capture timing. That is why we normally recommend the LVDS interface when operating at higher sample rates. Regards, Hooman

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