Forum Post: Interface between ADS58J98-EVM and Xilinx KCU105 Evaluation board
Hello, We've got a customer who wants to know if the ADS58J89-EVM will connect to the Xilinx KCU105 through the FMC connector without issues. They are specifically concerned that the U3B TTL has a 3.3V...
View ArticleForum Post: RE: LMH1251, wrong pulse width of V sync.
Hello Shinichi, The LMH1251 produces accurate H and V sync leading / rising edge, but the trailing / falling edge is set by RC delay (in certain cases) which may not be accurate enough. This is also...
View ArticleForum Post: RE: LMH1251, wrong pulse width of V sync.
Dear Hooman Thank you for your reply. In this case, Vsync pulse is produced by V, sometimes Vsync pulse width became twice. Is this an assumable result? The customer wants to know why this phenomenon...
View ArticleForum Post: RE: LMH1251, wrong pulse width of V sync.
Hi Shinichi, From talking to the designer, the answer I got was "the trailing edge is not going to occur at an accurate point, but the leading edge will be". Since he is no longer in my group,...
View ArticleForum Post: AFE5803 power mode setting and PGA gain
Hi, I would like to ask you a question about PGA gain as below. My customer has been evaluating AFE5803 and recently has a problem with PGA gain 30dB. They observed PGA gain 24dB correctly working but...
View ArticleForum Post: RE: LMH1251, wrong pulse width of V sync.
Dear Hooman Thank you for your quick reply. I understand It must use leading edge. I'll send your information to the customer. I appreciate your great help. Best regards, Shinichi
View ArticleForum Post: RE: AFE5808A clock input capacitance
Sorry Chen, I didn't mean to ignore you and this thread but I lapsed into an email chain with Xiaochen. Thanks for the help, and in case anyone else needs it below is the input model with all of the...
View ArticleForum Post: Question on the VPP/VNN voltatge description in the datasheet of...
Hi, I have a question about the VPP/VNN maximum rating of LM96551 . In the datasheet of LM96551 : In page 4, it says while in page 5, it says So, what is the range of VPP? -0.3V to 55V? 3.3V to 50V?...
View ArticleForum Post: RE: Question on the VPP/VNN voltatge description in the datasheet...
Hello Frank, I've moved this post from the Medical Forum to the Imaging AFEs Forum, where the LM96551 is supported. I'm sure you'll find an answer here.
View ArticleForum Post: RE: Question on the VPP/VNN voltatge description in the datasheet...
Hello Frank, The operating conditions you are asking about is what page 4 specifies (3.3V to 50V) and which is reiterated in the Operating Ratings table on page 5. The absolute maximum ratings are...
View ArticleForum Post: LM98725 - PLL Locking
Dear all, we have a processor in our design which will deliver the base IN_CLOCK for the two Analog Front-Ends LM98725 . One Analog Front End itself will lock the internal PLL to achive some desired...
View ArticleForum Post: RE: LM98725 - PLL Locking
Hi Christian, The latency through the device from INCLK to CLKOUT output will vary somewhat from part to part due to process variability, random mismatch, etc. For this reason you must use the CLKOUT...
View ArticleForum Post: How to synchronize two LM98722 AFEs
I am using a Contact Image Sensor (CIS) which has 6 analogue output taps. I'm planning to use 2 AFE chips LM98722 which have 3 analogue inputs each. I am supplying an external SH_R pulse to both AFEs...
View ArticleForum Post: RE: How to synchronize two LM98722 AFEs
Hi John, It should be possible to synchronize the LM98722 AFEs as you are intending. You will need to make sure that the SH_R input meets setup and hold timing with the applied INCLK of each device....
View ArticleForum Post: RE: How to synchronize two LM98722 AFEs
Thanks Hooman We will set the INCLK to pixel sampling rate and guarantee the setup and hold times for SH_R. Also we will add the Line# lsb and msb in the data stream for AFE2. Regards John
View ArticleForum Post: RE: AFE5808A clock input capacitance
Hello Roger, How are you? As you can see from the equivalent circuit of the clock diagram for the differential clock input signals (CLK+ and CLK-) of AFE5808A device. Their clock input impedances are...
View ArticleForum Post: Thermal protection of AFE5808A
Hi ! We are using AFE5808A in Ultrasound Imaging. Datasheet section 9.3.6 requires user to make sure junction temperature below 105 degree by using heat removal technique. Is there Thermal shutdown...
View ArticleForum Post: Need Help Configuring LM98722, not responding
Hi, I am using LM98722 with a Trilinear CCD in my application. The sensor timing is basically generated using FPGA . INCLK is 5 MHZ. R, G, B analog signals are connected to the IC. Serial communication...
View ArticleForum Post: Using LM98725
Hello experts, we are designing a prototype for our small xray system using cmos sensor M118-232C3. I want to know can we use LM98725 with this CIS module and how?
View ArticleForum Post: RE: Need Help Configuring LM98722, not responding
Hi Pranav, Can you share your schematic please? If you are trying to use slave mode and you do not have SH_R hooked up, it’s not going to work. Regards, Hooman
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