Hi Martin, We understand your usage needs better now. Since you are using the CIS in monochrome mode, with the same illumination color (X-ray) for every line, you should be using Mode 3, with a single line sequence. This is shown in Figure 48 of the datasheet. Since you don't need to turn the RGB lamps on then you don't need to enable or connect any of those signals. As your illumination is coming from outside the sensor, you should tie all of the lamp control pins of the CIS sensor to Ground so the sensor internal drive transistors are off. If your pixel sample rate is 5 MHz I recommend you use a 5 MHz pixel rate input clock to the LM98725 AFE. It will multiply this up by 3x to create the internal ADC clock. Once your have the sensor clocking working you can adjust the PIXPHASE, CLAMP and SAMPLE settings to align the AFE sampling event to the CIS pixel output timing. See Figure 24 and Figure 28 of the datasheet. Since this is a CIS sensor, you'll need to use S/H mode so the CLAMP and SAMPLE timings should be set the same. The reference voltage sampled is from the VCLP. CIS sensors like this one only require a single clock for the SP signal, once per line. CCD sensors can require much more complex Shift pulses (transferring charge from the pixel sensing array to the CCD transfer array). Sometimes the high resolution sensors even need different timing for different lines in their sequence. That is what the multiple SH interval feature is primarily intended for. For the CIS sensor you have, you just need to make the SP signal go high for 1 pixel period. So you probably will only have one SH interval with 1 or a few states. The SP signal will be programmed to be low during the line portion and high during a single pixel period in the SH interval. Since you are using CMOS data output mode, there isn’t any bit tag information sent to your FPGA. For that reason I recommend you also connect the PHIA1 signal to your FPGA. Alternatively we can make a duplicate of this signal on another output (SH1, etc.) to send to the FPGA. This will let the FPGA know when the start of line is for data alignment purposes. If you use a different SH output (than used for CP) you could program this signal to go high and low at the beginning and end of valid pixel data. I have attached a starting point register set for your needs. These settings would be loaded and then a final write to Page 0 Register 0 with value 0x23h must be done to Lock the registers and start AFE operation. (Please visit the site to view this file) Hope this helps. Regards, Hooman
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