I am having issues getting the test generation pattern to output anything on the LVDS lines. We are using our own board design, not an EVM. Here are our conditions: - 5V, 3.3V, 1.8V supplies are stable - Use Altera FPGA to control the AFE5809 - CLKP_ADC & CLKN_ADC using 40MHz single ended clock with series 100nF capacitor per datasheet - pdn_vca, pdn_adc, pdn_global, reset pins set to 0 via FPGA - sen pin set low during SPI transmission - spi_dig_en set high at all times - use software reset in SPI per section 8.6 in datasheet - FCLK is generated successfully, DCLK is not generated - the following 24bit words are sent to the ADC registers via SPI SDATA address 0x1: 01C000 address 0x2: 024000 address 0x3: 032000 address 0xA: 0A0100 address 0x16: 160001 - no SPI commands to the VCA registers or demodulation registers The SCLK and SDATA lines are working, as in they have information being transmitted. The D1-D2 LVDS lines have a DC value of 1.35V and .85V for the + and - lines, while the D3-D4 lines are centered at 1.1V. This suggest to me that the LVDS outputs are not doing the same thing. In addition, our FPGA code is set up so that it will detect a sync_word from the AFE, and right now there is no sync_word detected by the FPGA.
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