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Forum Post: RE: LM98620 eval board schematic

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Hi Prasanna For SH1a mode you can leave the DLL sample position settings at defaults. You do not need to drive the SHD/HOLD or SHP/SAMPLE inputs. The sample and hold timing is driven from AFEPHASE internal timing signal. I recommend you use a Pixel Rate input clock. Then the internal AFEPHASE timing is determined by the input clock and no other external timing signal is required. Best regards, Jim Bg

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