Hi folks, I'm working on a design with an AFE module where I'll be taking advantage of channel compression so that I'll have multiple channels multiplexed onto a single LVDS lane. I'll also be using the decimation feature such that the device will have several clock cycles of output between samples. One sample from each channel will be sequentially output on the single LVDS lane followed by several clock cycles of zeros. Then, when the next sample is available, again, one word from each channel will be multiplexed onto the lane followed by zeros. This repeats until we're done sampling. If I'm not mistaken, I believe the DCLK and FCLK continue to run between samples. Looking at this from the FPGA side where I'll be deserializing the samples, is there a preferred way to associate a sample with a channel? For example, do I simply count the number of frame cycles to identify what byte is associated with each channel, or is there some kind of reference signal that channel 1 is now being output? Thanks for any advice, Matt
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