Forum Post: RE: Clock input to CIS sensor from LM98722 AFE's CCD timing generation

Hi Hooman, Thanks for your Reply, As for the information required for you, i have attached the timing diagram for your reference. Note: Clock Frequency – 4 MHz Clock Duty Cycle – 50% Data Output Timing Chart: After turning on the SP pulse, the analog output starts from the setting up point of 83 clock pulse. Reading Colour Document: Thanks.... Regards, Gokuleswaran R