Hello Hooman, In the datasheet on page 87, Figure 66 & 67 shows that the SDI pin is receiving the data commands before the 9th clock but in the description its written that master will take control of SDI pin after the falling edge of the 9th clock. Secondly I'm also not reading the correct data values of the registers after configuration, I have sent you the register data file and I have also read the register data on oscilloscope but there is one problem when I configure the register 0 on page 0 at the end to lock the register bit and PLL bit but the data I read showed that only register bit is locked and PLL still unlocked. I send 0hA3 (1010 0011) to lock the registers and PLL but I received 0h23 (0010 0011). Thank you.
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