Forum Post: RE: ADS8638: channel sequencing in manual mode
Hi Nick, Please check the timing graph I highlighted in your another query as below, your understanding is correct. You can use DUMMY command but it will reduce your maximum sampling rate, actually it...
View ArticleForum Post: RE: SM73201-ARC-EV: RD 195 Safety Test Fail
Hello Ozino, Yes Newly assigned sections FLASHA for 6, FLASHC_1 is assigned for 3 and FLASHD_1 for just 1 information portions of the code. All the other one are assigned to1 to 3 regions. Thanks, Rahul
View ArticleForum Post: RE: SM73201-ARC-EV: RD 195 Safety Test Fail
Rahul, Can you attach a copy of your linker command file? Were there any build errors before adding the addtionial sections of FLASH to the .text field. Here is a wiki page regarding splitting memory:...
View ArticleForum Post: RE: SM73201-ARC-EV: RD 195 Safety Test Fail
(Please visit the site to view this file) Before adding the flash region this is the error. After addition of extra regions build was successful. without any errors. Please find the linker file I have...
View ArticleForum Post: ADS131A02: DRDY data line not behaving as expected
Part Number: ADS131A02 I'm currently trying to receive data from the ADS131A02DC, but am having a problem with the DRDY line. My hardware is set up such that M0 is HIGH (asynchronous interrupt mode),...
View ArticleForum Post: RE: ADS7223: CID in full clock mode
Ok, so PDE = 1 and M0 = 1? I'll have to talk with Tom Hendrick about what it could be. I'll get back to you soon. Regards,
View ArticleForum Post: RE: ADS1278: Code example
Hello Juan, You should configure your host SPI as master. You can either pole the /DRDY pin or use it to trigger an interrupt to clock out data. Once data is ready (/DRDY goes from high to low), you...
View ArticleForum Post: RE: ADS7049-Q1: SCLK input timing requirement
Hello, This timing requirement describes the high and low time of one square clock pulse. It ensures that the clock signal is a flow of equal square shapes, eliminating any arbitrary set of high or low...
View ArticleForum Post: RE: ADS7953: Misssing Codes
Hello, It sounds like the source of the issue is likely the reference. The reference input is compared to the input signal within the device to measure the output signal. If there is drift or...
View ArticleForum Post: RE: TLC7524: Bipolar Operation Mode & Reading the output
Hey, Yes I was. I found that I didn't need bipolar operation for my system, but now I'm in a small pickle because my output is not coming out as I would like. I am trying to create a sine wave from 0-5...
View ArticleForum Post: RE: ADS8671: ADS867x range switching time.
Hello, After completing a valid data transfer to configure the registers the next conversion should reflect the register configuration changes. The time this takes depends on the clock frequency used...
View ArticleForum Post: RE: ADS7953: Misssing Codes
Hi Cynthia, There was a small amount of noise on the 2V5A reference rail with the 330pF capacitor on its output, and there is some jitter when a sample is taken. I added a 1uF capacitor onto the output...
View ArticleForum Post: RE: ADS7049-Q1: SCLK input timing requirement
Thanks, I may send you an email when more discussion is needed.
View ArticleForum Post: RE: ADS5294: ADS5294EVM
hi chen, i have gone through the schematic of TSW1400EVM and the LVDS pins are connected to 2.5 V bank so we have to connect the FMC connectors pins of FPGA = KC705 to 2.5 V. is it right ? thanks and...
View ArticleForum Post: RE: ADS8671: ADS867x range switching time.
Hi alperen akk, Welcome to E2E Forum. If any of the commands to ADS8671 are provided in a particular data frame F, that command will get executed at the rising edge of the CONVST/CS signal. I...
View ArticleForum Post: ADS1256: Buffering for the ADS1256
Part Number: ADS1256 Hi Chris, I wonder if op amp buffering for the ADS1256 input is necessary and when do we use it for optimal performance Thank you, Khoi Ly
View ArticleForum Post: RE: ADS8671: ADS867x range switching time.
That's what I was looking for. Thank you very much.
View ArticleForum Post: RE: ADS1256: Buffering for the ADS1256
Hi Khoi, You are referring to the ADS1256 's internal input buffer, correct? Enabling the ADS1256 's internal buffer increases the input impedance of the ADC, is also causes a slight increase in noise....
View ArticleForum Post: RE: ADS1256: Power Drain during channel switching
Hi Muruga, Did you have additional questions regarding the AVDD voltage? I provided some guidance in a previous post (see: e2e.ti.com/.../751792) , but perhaps I should have clarified that running AVDD...
View ArticleForum Post: RE: ADS131E08: Low pass filter cut off frequency requirement...
Siva, The ADS131E08 is a delta-sigma or oversampling type of converter. This means that the device samples the input many times to give an output data. The ADC input samples at the modulator rate...
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