Hi Moti, There are knobs such as RBD (release buffer delay) and DAC output delay register that can be used to align the phase of all TX outputs provided there is a fixed delay between the outputs. If you can ensure SYSREF is sampled at the same time at all TX, then that is ok too since you can configure all the JESD and delay parameters in DAC the same. Yes, you need to distribute SYSREF to FPGA. The requirement is that SYSREF sampling at the FPGA by the device clock is deterministic but if you can ensure that SYSREF is sampled at the same time at the FPGA and all DACs, that is ok too. You may also use an AND gate to combine the SYNC~ from all DAC devices into one SYNC~ signal for the FPGA Thanks, Eben.
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