Hi Even, Thank you for your post. The issue I see with this proposal is that the FSYNC period from the master device (ADC0) is only long enough to fit 32 SCLKs, where the SCLK frequency that is output from ADC0 will be equal to exactly 32 x fDATA. When you daisy-chain 2 devices in Frame-Sync Mode, the FSYNC period from ADC0 will still match the data rate, but your SCLK will need to be twice as fast = 64 x fDATA in order to fit the data from both devices in the frame. Best Regards,
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