Hi Brian, 1) The purpose of tuning the PLL is to ensure the PLL stays locked over temperature. Without tuning, the PLL cannot be guaranteed to stay locked over temperature 3) Can you confirm how you are checking the results for the short pattern test? Section 2.8 of the app note below describes how the results for the short pattern test should be checked. www.ti.com/.../slaa750.pdf 5) 1 means invert and 0 means do not invert. It is possible the serdes IP in FPGA is configured to invert the serialized data Thanks, Eben.
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