Chen, Thanks for the reply. We managed to get the full chain "working" from analog input to LVDS output. When we input a sine wave to the AFE we can see data on the LVDS lines. I believe it should be safe to assume that the the sync word is embedded somewhere in there, however our FPGA is not detecting sync word and our FPGA PLL is not able to lock onto DCLK. Due to equipment bandwith limits, we are not able to see what DCLK is doing so we can't tell if it's the AFE sending a wrong DCLK or the FPGA PLL having an issue. What we are trying to do is set up for 16 bit operation, DCLK 8x of FCLK, with sync_word 0x2772. Other functions are not important at this time, we just want to receive analog signals and output digital signals at 8x operation. The register settings we are using are below. Please let us know if this is not the right setting to achieve the functionality listed above. addr 0x00: 0x0001 addr 0x01: 0xC000 addr 0x03: 0x2000 addr 0x04: 0x0010 addr 0x52: 0x117F addr 0xC3: 0x6800 addr 0xC4: 0x0010 addr 0xCA: 0x0212 Thanks, Wei-Han
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