Hi Martin, Some responses to your questions in color below. For my CIS sensor SP signal, I set only one SH state length i.e SH State 0 on Page 3 Register 0 and all other state lengths should be zero because I need signal to go high only once. Furthermore I select SH1 to go high at SH state zero (Page 5 Register 0 Bit 0 = 1) and connect this SH1 to my CIS SP signal pin. This is Okay? This sounds OK. If possible please share a schematic/sketch so we can verify the connections. My CIS sensor is getting CP from PHIA1, for this purpose I did following configuration: INCLK = PIXCLK = 5MHz This is correct. Page 6 Register 1E Bit 4 = 0 (for 5MHz PHIA) This is correct. But I don’t understand how should I configure registers 0 to 5 on page 6 for PHIA and what are their functions? You told me to configure them as well in your last message. There are 42 bit-times during one pixel period. The 42 bit pattern in these registers sets the output waveform of the PHIA timing generator for one pixel period. When the bits are 0s the output is low, and when the bits are 1s the output is high. For a simplistic case if the first 21 bits are 0 and the next 21 bits are 1 then the output waveform will be a 50% duty cycle square wave, which is the desired waveform for this sensor input. There is a description about CE pin (chip enable) on page 84 should I connect it to the GND? The CE pin can be logic low (DGND), logic high (connected to VD) or left open circuit (floating). The state of this pin determines the values of the 2 CE bits in the address field of the serial interface timing diagram. This allows multiple LM98725 devices to share a common SPI bus if needed. Regards, Hooman
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