Wei-Han, I am the applications engineer for the AFE5809 and I made the EVM and GUI, which I know that you are not using. The sync word and also 16-bit mode only work when you are using the DEMOD feature. The ADC in the AFE5809 is only a 14-bit ADC, but the decimation can effectively increase the resolution to 16 bits. Either way, in any mode you can use the 16x serialization which is separate but similar to the ADC resolution. For instance, you can use 14-bit ADC resolution and 16x serialization. So, please let us confirm the LVDS data without any use of the DEMOD function first, if you plan on using that. Therefore, there will be no sync word in the data and we can use 14b,14x mode for the data. This means that the FCLK will be at a frequency equal to Fs, and the DCLK will be at 14/2 *Fs, or 7 * Fs. If you can use a slower input clock than you can see if there is a speed or alignment issue, but I know that this is often difficult. Please use the Deskew pattern to debug the DCLK alignment, and the Sync pattern to debug the FCLK alignment. Chuck
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