Chuck, We managed to correctly output a custom pattern with sync_word by having the ADC set to custom test pattern mode and the demodulator operating normally. This was just for testing purposes, for the actual system we need to make corrections. I still have some confusion about the DCLK rate. For our project we are supplying a single-ended CLKP/N_ADC of 40MHz, combining LVDS output channels, 16x serialization, 4x decimation factor. We determined that this should result in an output data rate of 40MHz/4 * 32bits * 2 = 640Mbps on the combined channel. This would translate to DCLK of 320MHz, however, we observe that setting the register settings for LVDS 2x, 16x serialization, 4x decimation results in a DCLK of 640MHz. Could you clear up the confusion?
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