Wei-Han, If you are using the DEMOD, then you should see the sync word when a trigger is applied to the TX_sync_in pin. Data rate: This can confuse many people. Most ADC devices will reduce the output data rate with decimation. The AFE5809 is unusual because it does not reduce the output data rate (serial rate), but it does reduce the effective data rate and can interleave channels. Please see figure 67 of the datasheet. Whether the decimation is used or not, the serial rate does not change. If M=7, the serial output will be A.i, A.q, 0,0,0,0,0, A.i, A.q,.....In the FPGA, remove the 0s and deserialized the quadrature and the effective sample rate, Fs', for A.i will be Fs/7. Fs=40MHz, LVDS 1x, Serz Rate =16x, and any Dec Factor : DCLK will be at FCLK*16/2, so 40M*8=320M. Divide by 2 comes from the DDR nature of the data, SDR would not divide by 2. Both clock edges can be used to latch the data in DDR. For LVDS 2x mode, I believe the output data rate would double and there is 32 bits/FCLK instead of 16 bits/FCLK. Therefore, 320M * 2 =640M. Again, decimation does not help reduce this rate. With M=4, use the FPGA or processing device to separate the decimated data, throw away zeroes and de-interleave the channels, and each channel will have an Fs' = 10MHz, instead of Fs= 40MHz with M=1. Chuck Smyth
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