Forum Post: RE: ADS1298: Using ADS1298 and ADS1294R in daisy chain mode....
Hi Alex, Both devices have /CS tied together and both are driven Low during R/W. One thing we have missed out, is tying DAISY_IN to GND on the final device. On our current prototype DAISY_IN has been...
View ArticleForum Post: RE: DAC80508EVM: DAC80508EVM Altium Files?
Kevin, Excellent. Much appreciated - this will be used for our new design. Thank - Duncan
View ArticleForum Post: RE: Looking for an FPGA ADC
Hi Clayton What is driving the need for 18-bit? What are your SNR, SFDR requirements? Does your input signal need to be AC- or DC-coupled to the ADC? What is the signal voltage type (single-ended,...
View ArticleForum Post: RE: DAC38J84: DAC38J84: Internal PLL can not Locked
Henry, I have answered your question through TI internal FAEs email chain. I will close this issue on E2E. Please look for email from our TI team. -Kang
View ArticleForum Post: RE: ADS1115: ADC-Pro plug in
Haruo-san, The ADS1115EVM-PDK has been obsoleted for probably over a year, and we had the downloadable link for the software up until a couple of months ago. Because of this, we haven't tried to...
View ArticleForum Post: RE: ADS1231: Possible to turn off AVDD power supply while in...
Hi Ashton, Is there a particular reason why you want to turn off the AVDD supply? The analog supply only consumes about 100nA when in the powered down state. The ADS1231 was designed with the low-side...
View ArticleForum Post: RE: ADS1115: ADC-Pro plug in
Haruo-san, Another thought is to use the ADS1015EVM-PDK . This board will also be obsoleted, but the software is still currently available. We are in the process of putting together a new ADS1115EVM...
View ArticleForum Post: RE: ADS1282: Mux Channel Switching
Hi Santosh, What is the command sequence you are using for the WREG command to the CONFIG1 register? Is it possible that in the WREG command you are setting the "nnnnn" bits to a non-zero value? In...
View ArticleForum Post: RE: ADS1218: Queries related to PGA and calibration commands- reg
Makesh, 1. The PGA is basically a programmable gain amplifier. It allows for the measurement of smaller signals so the resolution is better. For the measurement using a 2.5V reference: PGA=1:...
View ArticleForum Post: RE: ADS1263: External clock issue
Hi Ed, Welcome to the TI E2E Forums! Do you happen to have a schematic of the ADS1263 in your problematic circuit that you could share? I am currently wondering how you have the ADC grounds...
View ArticleForum Post: RE: DAC60508: Buffered Input
Hi Matt, Yes, the DAC output will remain at the previous value until the SPI transaction is complete and the new data is latched into the DAC data register. This occurs on the rising edge of CS in...
View ArticleForum Post: RE: DAC38J84: eye scan via Jtag
the first link doesn't seem to work. I did get a box drop from my FAE. the problem is the usb-jtag interface. I need 1.8v I/o on jtag, so the FTDI chip won't work for the dongle. the Xilinx dongle...
View ArticleForum Post: RE: ADS1231: Do we have example C code for ADS1231?
Richard, We've recently gone through some changes on how we release software. However this file should still be available. Go to the landing page for the ADS1231REF , which you can find here:...
View ArticleForum Post: RE: ADS1292ECG-FE: ADS1292ECG-FE
Thanks for the reply and yes I am following up the User's guide. Also when I open the ADS1x9x ECG-FE application a popup window shows up with the following message: "An error occurred with error code...
View ArticleForum Post: RE: ADS1231: Do we have example C code for ADS1231?
Richard, I've been told that this software is just for the GUI to run the board, and not the actual firmware zip that we used to have on the ftp site. At this point, we don't have any example code...
View ArticleForum Post: RE: ADC12DJ3200: The SYNC signal between ADC and Xilinx FPGA not...
Hi junsha Have you made any progress on this, to determine why the FPGA is asserting and de-asserting SYNC when you don't expect that to happen? Please confirm if the problem is resolved. Regards, Jim B
View ArticleForum Post: RE: ADC12J1600: ADC12J1600 to KC705 FPGA: Verilog code
Hi Jim, Looks like what I need. I will go through the code. Thank you so much.
View ArticleForum Post: RE: ADS1292ECG-FE: ADS1292ECG-FE
I was just checking issues with other folks and there were some mention on limitation of the window 8 or so. I am using this eval kit with windows 10 and I was wondering if this kit is operational with...
View ArticleForum Post: RE: DAC38J84: LMF=211 mode
Thank you Kang Hsia for your quick response. It is good to know that it is working with LMF=211 setting. Now, my questions is about other register settings. How did you set the following registers in...
View ArticleForum Post: RE: DAC38J84: LMF=211 mode
Correction to my previous post! M should be corrected as 1 in the line which contains "What does happen if I set L=2 M=2 F=1 in config75/76/77 with your current setting?"
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